The present invention generally relates to the manufacture of fine structures that is required in semiconductor technology for various applications.
In view of increasing miniaturization, masks with finer and finer structures are required in semiconductor technology. The masks are employed as etching masks or implantation masks.
Further, the manufacture of fine structures that remain as an active or passive component part in the component or in the arrangement to be manufactured is often required. This is true both of microelectronic components or arrangements as well as of micromechanical components or arrangements.
For example, such a component, which is suitable as volatile and non-volatile memory, has been proposed in an article entitled: "Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage" (S. Tiwari et al., IEDM 95, pp. 521-524). As a memory cell, the component has a MOS transistor in whose gate dielectric includes what are referred to as silicon nano-crystals that are provided as charge storages. What are thereby involved are small silicon crystals having diameters of 5 nm that are embedded in a matrix of SiO.sub.2. Charge is stored in these silicon crystals; this charge--similar to the stored charge on a floating gate of an EEPROM--influences the cutoff voltage of the MOS transistor. SiO.sub.2 arranged under the silicon crystals thereby acts as tunnel oxide. The silicon crystals are formed by spontaneous decomposition and combination of materials in CVD depositions. Size and packing density of the arising silicon crystals are thereby difficult to control.
The present invention is, therefore, based on the problem of specifying a method for the manufacture of fine structures wherein the packing density of the fine structures can be set better. Over and above this, the size of the fine structures should also be adjustable.